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- Notes on the AGX Server
-
- Henry Worth
-
- 24 June 1995
-
-
-
- 1. General Notes
-
- This server currently supports the IIT AGX-016, AGX-015, AGX-014 and XGA-2
- chipsets. The AGX chipset is based on XGA architecture, but is missing several
- features and differs on others. There's also untested support for the XGA-1 and
- AGX-010 chipsets. Pixel depths of 8bpp, 15bpp, 16bpp are generally supported.
- Unpacked 24bpp (RGBX 32bpp) is not yet stable enough to release.
-
- RAMDACs currently supported are the Brooktree (BT481, BT482, and BT485) and
- AT&T (20C505) RAMDACs used by the Hercules Graphite series, and Sierra RAMDACs
- (15025 and 15021), and Generic VGA RAMDAC. Untested support has been added for
- the AT&T 20C490 series.
-
-
- The current driver has a number of acceleration routines: solid and dashed
- zero-width lines (except AGX-014), bitblt fills, tiles, and stipples, solid arc
- and polygon fills, character glyphs and font cache for 8-bit characters.
-
- Boards that have had some testing include ISA and VLB versions of most of the
- Hercules Graphite series, Spider Black Widow VLB and Black Widow Plus VLB, Boca
- Vortek VL, CatsEye/X XGA-2, and the PS/2-57 planar XGA-2. The Orchid Celsius is
- very similar to the Spider and Boca boards, except some batches may use one of
- the AT&T 20C490 series RAMDACs, instead of the Sierra 15025. There has also
- been a report of a generic board that uses a UMC RAMDAC that may be an AT&T
- 20C490 Clone.
-
-
- 2. Acknowledgments
-
- First, to Hercules Customer Support for providing a loaner board to get things
- started.
-
- Second, to the XFree86 team, and those who who have contributed to their
- efforts to the project, for the foundation of work that provided a basis for
- bootstrapping this server.
-
-
- 3. Known Problems
-
- o The accelerated line routines don't match lines written by the mi/cfb rou-
- tines. This is noticeable when switching between virtual consoles while
- running routines that draw and erase lines. Seems to have been
- reduced/fixed in previous releases but need more testing.
-
-
-
- Notes on the AGX Server
-
-
-
-
-
- Notes on the AGX Server
-
-
-
- o Some special-case speedup added to cached font rendering in 3.1.1 has been
- disabled as is over-aggressive in some cases. This cuts the performance on
- terminal-fonts in half, and font performance is already low for the AGX
- chips compared to their contemporaries.
-
- o As in all software, needs more testing.
-
-
- 4. ToDo
-
- o Address the above known problems.
-
- o Additional acceleration routines and general performance improvements.
- Many existing acceleration routines are Q&D adaptations of existing rou-
- tines from other servers that support graphics chips that differ signifi-
- cantly, architecturally, from that XGA and are undoubtedly less than opti-
- mal. In particular some of the general per-operation overhead to set-up
- the graphics context should be moved to the ValidateGC() routines.
-
- o Complete HW cursor support, most of the code is done (or borrowed from
- other servers). There just remains a little setup code and then finding a
- lot of time to debug and test the numerous permutations.
-
- o Complete support for the Graphite Pro's 84-pin RAMDAC. (the 2MB version
- of the Graphite Pro has both RAMDACs, the 1Mb only the 44-pin RAMDAC).
- Currently, the 84-pin RAMDAC is only supported in clock-doubled pixmux
- mode, the server will switch between RAMDACs as required by the video mode
- In >8bpp modes this switching does not occur.
-
- o Implement more HW probing, this will be difficult as it appears some
- (all?) AGX-based vendors don't implement the VESA VXE POS registers,
- although the AGX chip does support it (and some vendors claim VXE compli-
- ance...). There are a few rev/vendor registers in the AGX chip but they
- are not documented. Note: SuperProbe also does not support probing for
- AGX/XGA chips. ISA POS probing is supported for the XGA chips and some
- code for EISA POS is also included but not tested.
-
- o Micro-optimizations, in particularly reducing processing overhead for com-
- mon special cases that don't require full generality.
-
-
- 5. XF86Config
-
-
- Device Section Entries and Options Currently Supported:
-
- The minimum that must be specified in the XF86Config device section for the
- AGX-014, AGX-015, AGX-016, and ISA-based XGA-1 and XGA-2 is the Chipset. How-
- ever to get full capability out of the AGX-01[456] chips, the RAMDAC should be
- specified. Other parms may select additional capabilities, or may used to
- override the defaults or reduce start-up time be suppressing probing. XGA spe-
- cific configuration is covered at the end of this document. The XGA entries can
- generally be used to override defaults for the AGX-01[456] as well.
-
-
-
-
-
-
-
-
-
- Notes on the AGX Server
-
-
-
- Ramdac
- Be sure to check the clock rating of the RAMDAC(s) on your video
- board and don't exceed that rating even if the server allows it,
- overclocking RAMDACs will damage them.
-
- The clock rating generally appears as a suffix to the part number,
- may only have the most significant digit(s), and may be mixed with
- other codes (e.g. package type). For example, an 85MHz Bt481 in a
- plastic J-lead package has a part number of Bt481KPJ85 and a 135MHz
- AT&T20C505 has a part number of ATT20C505-13. Sierra stamps the
- rated speed below the part numbers in a dark ink.
-
- "normal"
- normal VGA style RAMDAC (6-bit DAC), default if none
- specified. Most boards should work with this parm, but
- some capabilities will be unavailable. Only 8bpp is
- available.
-
- "bt481"
- bt481 RAMDAC (supports 8-bit DAC)
-
- "bt482"
- bt482 RAMDAC (supports 8-bit DAC) The Hercules Graphite
- HG210 uses the BT481 or BT482, the only difference
- between these two is the BT482's HW cursor (not yet
- supported). The BT481/2 are limited to 85Mhz. 8bpp,
- 15bpp, 16bpp are supported.
-
- "ATT20c490"
- AT&T490 RAMDAC (includes 49[123] - supports 8-bit DAC).
- Limited to 110Mhz at 8bpp. 8bpp, 15bpp, and 16bpp are
- supported.
-
- "SC15025"
- Sierra SC15025 and SC15021 RAMDAC (support 8-bit DAC).
- The SC15025 is limited to 125Mhz, and the SC15021
- 135Mhz. Check the RAMDAC's actual rating, some
- SC15025's used in AGX based boards are only rated to
- 110Mhz. 8bpp, 15bpp, and 16bpp are supported.
-
- "herc_dual_dac"
- Hercules Graphite Pro RAMDAC probe. If the 84-pin Big-
- RAMDAC is installed (2MB models), will use the Big RAM-
- DAC, but only clocks-doubled, pixel- multiplexed modes
- (higher clock values only!). Lower clocks and resolu-
- tions in 8bpp mode are supported by switching to the
- Small 44-pin RAMDAC. 15bpp and 16bpp are supported.
-
- There has been one report of the "dac-8-bit" option not
- working with a Graphite Pro equipped with a BT485 RAM-
- DAC, puzzling since it should be identical to the
- AT&T20C505 in this regard. No startup messages or
- XF86Config were submitted to aid problem isolation.
-
-
-
-
-
-
-
-
-
- Notes on the AGX Server
-
-
-
- Not supported by the HG210 Graphite.
-
- "herc_small_dac"
- Hercules Graphite Pro RAMDAC probe. Forces use of only
- the BT481/482 RAMDAC. 8bpp, 15bpp, 16bpp, and unpacked
- 24/32bpp are supported.
-
- Not supported by the HG210 Graphite.
-
- "xga"
- To allow overriding the default VGA style RAMDAC con-
- trol for the AGX-010.
-
-
- Ramdac related Option Flags:
-
- "dac_6_bit"
- Sets RAMDAC to VGA default 6-bit DAC mode (default for
- "normal").
-
- "dac_8_bit"
- Sets supported RAMDAC's to 8-bit DAC mode (default for
- all but "normal").
-
- "sync_on_green"
- Composite sync on green for RAMDAC's that support this
- feature (BT481/481 and AT&T20c490). However, whether
- any boards have necessary traces and glue logic is
- doubtful.
-
-
- Chipset:
- Must be specified, possible values: "AGX-016", "AGX-015",
- "AGX-014", "AGX-010", "XGA-2", or "XGA-1". Some AGX vendors place
- stickers over the chip, in general, if it's a VLB board it's proba-
- bly an AGX-015 and if it's an ISA board it may be an AGX-014. The
- Hercules Graphite Power Pro and Spider Black Widow Plus use the
- AGX-016 chipset. In general, specifying a lower revision in the
- AGX-0{14,15,16} series does not seem to causes problems (except
- lower performance from the AGX-014's non-accelerated line drawing).
-
- Note: Only the AGX-016, AGX-015, AGX-014 and XGA-2 have had any
- testing. Most of the development has been with an AGX-015 based 2MB
- Hercules Graphite VL PRO (HG720) and most of testers for previous
- releases had AGX-014 based 1MB Hercules Graphite (HG210).
-
- The limited documentation I have for the AGX-010 is that is is a
- clone of the XGA architecture with a few additional configuration
- registers. What is not clear is whether to use XGA or extended-VGA
- RAMDAC control registers. The post-3.1.1 default is now VGA con-
- trol registers, but XGA control registers can be forced with the
- XGA RAMDAC parm. Likewise the configuration parms described in the
- XGA section can be used to override the AGX defaults for I/O and
- memory addresses.
-
-
-
-
-
-
-
-
- Notes on the AGX Server
-
-
-
- VideoRam:
- Will be probed if not specified. The startup will be a little
- faster if specified.
-
- Tuning Option flags:
-
- Bus I/O interface:
-
- "8_bit_bus"
- Force 8-bit I/O bus.
-
- "wait_state", "no_wait_state"
- Set or clear CPU access wait state, default
- is the POST setting.
-
- "fifo_conserv"
- Disable Memory I/O Buffer, AGX-015 and
- AGX-016. MS-Windows driver default.
- Required by some VLB systems with `aggres-
- sive timing'. The default for this server
- is to disable the buffer.
-
- "fifo_moderate"
- Enable the AGX-015/016's Memory I/O buffer.
-
- "fifo_aggressive"
- Enable the AGX-016's extra-large buffer.
- Either option may result in garbage being
- left about the screen, disabled by default.
- A good test is the xbench or x11perf dashed
- lines tests, if random dots are drawn,
- fifo_conserv is required. So far, no boards
- have been reported that worked correctly
- with the buffers enabled.
-
- Memory Timing:
- POST defaults should be ok.
-
- "vram_delay_latch", "vram delay_ras", "vram_extend_ras"
- Vram timing options.
-
- "slow_vram", "slow_dram"
- Set all of the vram timing options.
-
- "med_dram"
- Set vram latch delay, clear others.
-
- "fast_vram",
- "fast_dram"" All of the vram timing
- options are cleared. Should be specified
- if directly specifying VRAM options in
- order to clear POST settings.
-
-
-
-
-
-
-
-
-
-
- Notes on the AGX Server
-
-
-
- Debugging:
- These shouldn't generally be required:
-
- "noaccel"
- (AGX,XGA) Disable Font Cache.
-
- "crtc_delay"
- (AGX) Force XGA mode CRTC delay.
-
- "engine_delay"
- AGX-015 only? adds additional VLB wait
- state.
-
- "vram_128", "vram_256"
- Sets VRAM shift frequency, vram_128 is for
- 128Kx8 VRAM. Default is to leave this bit
- unchanged from POST setting.
-
- "refresh_20", "refresh_25"
- Number of clock cycles between screen
- refreshes. Default is to leave this bit
- unchanged from POST setting.
-
- "screen_refresh"
- Disable screen refresh during non-blanked
- intervals, AGX-016. Default is leave them
- enabled.
-
- "vlb_a", "vlb_b"
- VLB transaction type, default is to leave
- this bit unchanged from POST value.
-
-
- Virtual resolution:
- The server now accepts any virtual width, however the actual usable
- CRTC line width is restricted when using the graphics engine and
- depends upon the chip revision. The CRTC line width and not the
- virtual width determine the amount of memory used. The server cur-
- rently does not make use of any of the unused CRTC line's memory.
- CRTC line width is restricted by the following rules:
-
- AGX-014 : 512, 1024 and 2048. (also AGX-010)
-
- AGX-015 : 512, 1024, 1280, and 2048.
-
- AGX-016 : 512, 640, 800, 1024, 1280, and 2048.
-
- XGA,AGX-010 : 512, 640, 800, 1024, 1280, 1152, and 2048.
-
- When panning I occasionally get streaks if the virtual resolution
- is much greater than the physical resolution. Moving the mouse a
- little makes it disappear. The Hercules manual indicates this also
- happens with the MS-Windows drivers.
-
-
-
-
-
-
-
-
-
- Notes on the AGX Server
-
-
-
- The server requires at least a 64KB scratchpad (16KB for XGA's).
- Additional memory is useful for font cache and a larger scratchpad.
-
- AGX Clocks:
- Probing is supported, but of course the usual warnings and dis-
- claimers apply. Probing may momentarily subject your monitor to
- sweep frequencies in excess of its rating. The cautious may wish
- to turn off the monitor while the probe is running.
-
- Once clocks are known, they can be entered into XF86Config, then
- subsequent runs won't probe clocks and will be quicker to startup.
- For the clock probe it is recommended that the X server be run with
- the -probeonly option. The values in the clocks statement are the
- hardware input clocks and correspond to the pixel clock only at
- 8bpp in direct-clocking RAMDAC modes. The server will divide/multi-
- ply those values as appropriate for the RAMDAC modes available at
- the current pixel depth. The available pixel clocks will be dis-
- played in the startup messages.
-
- For the 2MB Hercules Graphites, with the "herc-dual-dac" RAMDAC
- specified, earlier versions of the server generated an additional
- 16 clocks with values doubled and some zeroed. Those are no longer
- needed and you should re-probe and re-enter the clock values to
- ensure all clocks are available to you.
-
- The AGX-015 2MB Hercules Graphite VL Pro with an ICS1494M 9251-516
- clock chip has probed clock values of:
-
- 25.18 28.80 32.70 36.00 40.00 45.00 50.40 64.70
- 70.10 76.10 80.60 86.30 90.40 95.90 100.70 109.40
-
-
- Actual values according to Hercules are:
-
- 25.175 28.322 32.512 36.000 40.00 44.90 50.35 65.00
- 70.00 75.00 80.00 85.00 90.00 95.00 100.0 108.0
-
-
- These are the values to be used in the clock statement if specify-
- ing the "normal", "bt481", or "herc_small_dac" RAMDAC in your
- XF86Config and your clockchip matches that above.
-
- Clock probing assumes that the first clock is 25.175Mhz and uses
- that to derive the rest. A warning is displayed if the second is
- not near 28.322Mhz. If this warning appears, you should not use the
- probed clock values without additional verification from other
- sources.
-
- In the case of the AGX-014 and later AGX's, only the external clock
- select lines are used, this means the clock values correspond to
- the values of the video board's clock chip.
-
- For the AGX-010, the first 8 clocks use the standard XGA internal
- clock selects and the second 8 are based on AGX extensions. For the
-
-
-
-
-
-
-
-
- Notes on the AGX Server
-
-
-
- XGA-1 only 8 clocks are available. The XGA-2 uses a programmable
- clock and no clocks or clockchip line is required.
-
- The maximum pixel clock generally allowed is 85MHz, but some RAM-
- DACs support higher values. In any case you, should check your RAM-
- DAC, some RAMDACs used on AGX based boards are produced in versions
- rated to lesser values than the server assumes. You should check
- the rating and limit yourself to that value.
-
- Modes:
- One difference I've noted from the Mach8, is that the AGX's CRTC
- doesn't like the start of the horizontal sync to be equal to horiz
- blank start (vert sync may have the same problem, I need to test
- some more). Interlaced and +/-sync flags are supported but have had
- very little testing. For interlaced modes make sure the number of
- lines is an odd number.
-
- The doublescan flag is now supported, however the minimum clock
- supported is generally 25MHz, so resolutions of less than 400x300
- are not likely to be supported by most monitors. In creating dou-
- blescan mode timings, the vertical timings will match the apparent
- resolutions, e.g. for 400x300 the timings should describe 300
- lines, not 600.
-
- Examples:
-
- For the Hercules HG720 (2MB VLB AGX-015, with BT481 and
- AT&T20C5050 RAMDACs), I use the following XF86Config "Device" sec-
- tion:
-
- Section "Device"
- Identifier "HG720"
- VendorName "Hercules"
- BoardName "Graphite VL Pro"
- Chipset "AGX-015"
- Clocks 25.2 28.3 32.5 36.0 40.0 45.0 50.4 65.0
- 70.00 75.00 80.00 85.00 90.00 95.00 100.0 108.0
- Videoram 2048
- RamDac "herc_dual_dac"
- Option "dac_8_bit"
- Option "no_wait_state"
- EndSection
-
-
- For the Spider Black Widow Plus (2MB VLB AGX-016, with Sierra
- SC15021 RAMDAC):
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- Notes on the AGX Server
-
-
-
- Section "Device"
- Identifier "SBWP"
- VendorName "Spider"
- BoardName "Black Widow Plus"
- Chipset "AGX-016"
- Clocks 25.2 28.3 39.9 72.2 50.0 76.9 36.1 44.8
- 89.0 119.8 79.9 31.5 110.0 64.9 74.9 94.9
- Videoram 2048
- RamDac "SC15025"
- Option "dac_8_bit"
- Option "no_wait_state"
- EndSection
-
-
- 6. Xga configuration
-
- This server now has tested support for XGA-2 compatible boards (aka.
- XGA-NI). The main issue for XGA-1 support is whether clock probing works. At
- this time probing for board configuration is limited and detailed configuration
- may need to be done manually.
-
- By default the ISA POS register will be performed. If the XGA Instance
- number is specified the scope of probing will be narrowed a bit. To override or
- disable probing, a minimum of the Instance, COPbase, and MEMbase must be speci-
- fied in the XF86Config device section for the XGA card. MCA probing is not sup-
- ported.
-
- Instance nn
- XGA instance number (0-7).
-
- IObase nnnn
- The I/O address of the the XGA general control registers. The stan-
- dard, and default, is 0x21i0, where i is the instance number.
-
- MEMbase nnnn
- The XGA display memory address (the address the XGA coprocessor
- uses for video memory). This is also the system memory address of
- the linear aperture on boards that support it.
-
- POS register 4 bits 7-1 contains bits 31-25 of the XGA's display
- memory address. Bits 24-22 of of the display memory address con-
- tains the XGA instance number. Bit 0 of POS register 4 is not used
- by this server as the XGA's linear aperture is not used. However,
- the coprocessor must still be configured with this.
-
- The AGX-01[456] chips have a fixed display memory address.
-
- COPbase nnnnnn
- Address of the graphics engine's memory mapped control registers.
-
- Typically:
-
- 0xC1C00 + (ext_mem_addr * 0x2000) + (instance * 0x80)
-
-
-
-
-
-
-
-
-
- Notes on the AGX Server
-
-
-
- where ext_mem_addr is the high order 4-bits of POS register 2 (0-16
- the server assumes zero).
-
- The AGX-01[456] chips support 0xB1F00 (default) and 0xD1F00.
-
- BIOSbase nnnnnn
- Address of the XGA BIOS (not VGA BIOS). Can be specified as an
- alternate to COPbase.
-
- Typically:
-
- 0xC0000 + (ext_mem_addr * 0x2000)
-
- where ext_mem_addr is the high order 4-bits of POS register 2 (0-16
- -- the server assumes zero).
-
- VGAbase nnnn
- Can be used to override the default 0xA0000 address for the 64KB
- video memory address used by the server. The only values acceptable
- are 0xA0000 and 0xB0000. VGA text mode restore does not work under
- Linux if 0xB0000 is specified.
-
- AGX-01[456] also default to 0xA0000.
-
- POSbase nnnn
- Can be used to specify an alternate POS register probe address base
- from the ISA default of 0x100. The VESA VXE standard for EISA is
- 0xzC80, where z is the slot number).
-
- A value of zero will disable POS register probing (required for
- MCA).
-
- DACspeed nnnn
- Can be used to override the servers default maximum Pixel Clock for
- XGA-2 of 80Mhz. The limit can be raised as high as 90Mhz, or set
- to lower values.
-
- An alternate way to determine the POS register values is with the
- setup/diag programs that should have been included with your video board, or
- possibly from jumper values.
-
-
- The XGA-2 has programmable clocks up to 90MHz, however at 1024x768, 72MHz is
- generally the max that will produce a stable display with the CatsEye/XGA-2
- used for testing (IBM coprocessor and INMOS RAMDAC/serializer). Higher clocks
- will often generate artifacts at the top and left edges of the screen. Such
- artifacts can sometimes be tuned out by increasing the vertical and horizontal
- blanking intervals or slightly changing the clock. At pixel clock rates above
- 80Mhz I have seen the chip lose sync after running for several minutes, so
- 80Mhz has been set as the default limit for XGA-2 pixel clocks. I don't have
- specs on actual limits, and as there are a number of different XGA chipsets,
- you should use the modes documented in your owner's manual as a guide to max
- refresh rates. No clocks or clockchip parm are required to specify use of pro-
- grammable clocks for the XGA-2.
-
-
-
-
-
-
-
-
- Notes on the AGX Server
-
-
-
- 8bpp and 16bpp are supported for the XGA-2.
-
- For XGA-1 cards the clocks must be specified as for the AGX chips, it is not
- known whether the clockprobing will work. Some XGA-1 chips may support 16bpp.
-
- Generated from XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/agx.sgml,v 3.19 1997/01/25 03:22:19 dawes Exp $
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- CONTENTS
-
-
-
- 1. General Notes ............................................................ 1
-
- 2. Acknowledgments .......................................................... 1
-
- 3. Known Problems ........................................................... 1
-
- 4. ToDo ..................................................................... 2
-
- 5. XF86Config ............................................................... 2
-
- 6. Xga configuration ........................................................ 9
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